What happened
A Low-Power Mixed-Signal Differential In-Memory Matrix–Vector Computing Circuit Architecture with RISC-V Control for Edge AI
SourceMultidisciplinary Digital Publishing InstitutepublicationAI
A Low-Power Mixed-Signal Differential In-Memory Matrix–Vector Computing Circuit Architecture with RISC-V Control for Edge AI
Publication signal: A Low-Power Mixed-Signal Differential In-Memory Matrix–Vector Computing Circuit Architecture with RISC-V Control for Edge AI
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Recent source-backed research output for AISci Stage A browsing.
SourceMultidisciplinary Digital Publishing InstituteLimitations
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SourceMultidisciplinary Digital Publishing InstituteLinked output
A Low-Power Mixed-Signal Differential In-Memory Matrix–Vector Computing Circuit Architecture with RISC-V Control for Edge AIpaperPeople
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A Low-Power Mixed-Signal Differential In-Memory Matrix–Vector Computing Circuit Architecture with RISC-V Control for Edge AI
A Low-Power Mixed-Signal Differential In-Memory Matrix–Vector Computing Circuit Architecture with RISC-V Control for Edge AI
Compute and Hardware
Controlled AISci Stage A topic for Compute and Hardware.
Timeline
- publicationA Low-Power Mixed-Signal Differential In-Memory Matrix–Vector Computing Circuit Architecture with RISC-V Control for Edge AI