Compute and Hardware

A Low-Power Mixed-Signal Differential In-Memory Matrix–Vector Computing Circuit Architecture with RISC-V Control for Edge AI

Publication signal: Heterogeneous Network-on-Chip Design with Adaptive Key Rotation Aware Obfuscation

A Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators

Semiconductor Nanotechnology and Advanced Materials for Photonic AI Chips and Quantum Information Systems

Cross-Layer Design of Vector-Symbolic Computing: Bridging Cognition and Brain-Inspired Hardware Acceleration

Modular VLSI Neural Accelerator with Lightweight Activations for Sudden Cardiac Arrest Detection

Publication signal: Machines and Exascale computing

Bridging Quantum Computing Paradigms toward Semiconductor Yield: A Controlled CV-versus-DV Comparison on Wafer-Map Defect Classification

Secure Speech Communication via Syllable-Level Encryption and PUFBased Key Management in Edge Computing

Review of optical pre-sensor computing