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A Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators
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A Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators
Publication signal: A Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators
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A Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators
A Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators
Compute and Hardware
Controlled AISci Stage A topic for Compute and Hardware.
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- publicationA Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators