Verified by AISci
Public source attached
Source status for this paper in the current AISci reviewed snapshot.
- Primary source
- IOP Publishing
- Correction status
- none
- Evidence coverage
- 1 sources / 1 publishers
- Last metadata check
- Jul 19, 2026
paperAI
A Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators
A Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators
Source-permitted summary
A Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators
SourceIOP PublishingAI Reading Notes
Core signal
Structured notes generated from source-linked AISci metadata. Treat them as a reading aid, not a substitute for the paper.
- Core signal
- A Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators
- Field context
- Compute and Hardware
- People and labs
- Not stated in the reviewed source.
- Why it matters
- Recent source-backed research output for AISci Stage A browsing.
- Limits to check
- AISci rank score does not assess scientific quality or citation impact.
Research Workflow
Research Workflow
Recommended next steps for turning this signal into research action.
- Read original source
- Check DOI/OpenAlex
- Open relationship graph
- Review people and labs: Not stated in the reviewed source.
- Open linked event for AISci context
- Prepare journal-club PPT: AISci action coming next
- Plan replication checks: AISci action coming next
Publication facts
- Type
- paperSourceIOP Publishing
- Date
- Jul 2, 2026SourceIOP Publishing
- Venue
- Engineering Research ExpressSourceIOP Publishing
- Open access
- unknownSourceIOP Publishing
External IDs
Author order
No reviewed author edge is attached to this output.
Organizations
No source-confirmed author affiliation is attached.
Related events
Topics
Relationship evidence
Compute and Hardware
Controlled AISci Stage A topic for Compute and Hardware.
A Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators
Publication signal: A Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators
Timeline
- paperA Sparsity-Aware Zero-Bypass Vedic Multiplier MAC Architecture for Energy-Efficient CNN Hardware Accelerators